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CXP844P16 CMOS 8-bit Single Chip Microcomputer Description The CXP844P16 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, 32kHz timer/counter, remote control reception circuit and other servo systems besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port. The CXP844P16 also provides and a sleep/stop function that enables lower power consumption. This IC is the PROM-incorporated version of the CXP84416 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for smallquantity production. 80 pin QFP (PIastic) Features * Wide-range instruction system (213 instructions) to cover various types of data. -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation 122s at 32kHz operation * Incorporated PROM capacity 16Kbytes * Incorporated RAM capacity 448bytes * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32s/10MHz) -- Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 2 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter -- Remote control reception circuit Incorporated 6-stage FIFO 8-bit measurement counter -- PWM output for tuner 14 bits, 1 channel * Interruption 12 factors, 12 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 80-pin plastic QFP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E93908-ST Block Diagram AVREF AVss PE3/NMI AN0 to AN7 SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL 8 A/D CONVERTER PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 TEX TX EXTAL XTAL RST VDD Vss Vpp 8 PA0 to PA7 8 PB0 to PB7 PE4/PWM 14 BIT PWM GENERATOR 8 PC0 to PC7 INTERRUPT CONTROLLER PE2/RMC REMOCON FIFO ROM 16K BYTES RAM 448 BYTES 8 PD0 to PD7 4 2 PORT E PORT D PORT C PORT B PORT A PE5/TO 2 8 BIT TIMER 1 PORT H PORT G PORT F PE5/ADJ PORT I -2- FIFO 2 PE0 to PE3 PE4 to PE5 8 SERIAL INTERFACE UNIT 0 PF0 to PF7 32kHz TIMER/COUNTER PRESCALER/ TIME BASE TIMER PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 PB0/CS1 PB6/SI1 PB7/SO1 PB5/SCK1 8 PG0 to PG7 PE0/EC 8 BIT TIMER/COUNTER 0 8 PH0 to PH7 8 PI0 to PI7 CXP844P16 CXP844P16 Pin Assignment (Top View) PF2 PF1 PF0 PG7 PG6 PG5 PG4 Vpp VDD PG3 PG2 PG1 PG0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/ADJ PE4/PWM PE3/NMI PE2/RMC PE1 PE0/EC PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CS1 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PI7 PI6 PA1/AN1 Note) NC (Pin 73) must be connected to VDD. -3- PA0/AN0 PA2/AN2 EXTAL AVREF XTAL AVSS RST PH3 PH4 PH5 PH6 PH7 TEX VSS TX PI5 CXP844P16 Pin Description Pin code I/O (Port A) 8-bit I/O port. I/O can be set in single bit units. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) Functions PA0/AN0 to PA7/AN7 I/O/analog input Analog inputs to A/D converter. (8 pins) PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O/input I/O/input I/O/I/O I/O/input I/O/output I/O/input/output I/O/input I/O/output (Port B) 8-bit I/O port. I/O can be set in single bit units. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH1). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. Incorporation of pull-up resistor can be set through the software. (8 pins) PC0 to PC7 I/O PD0 to PD7 I/O PE0/EC PE1 PE2/RMC PE3/NMI PE4/PWM PE5/TO/ADJ Input/input Input Input/input Input/input Output/output Output/output/ output Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/ counter (duty output 50%). Output for 32kHz oscillation frequency demultiplication. PF0 to PF7 I/O (Port F) 8-bit output port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) -4- CXP844P16 Pin code I/O Functions (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit output ports. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. PG0 to PG7 I/O PH0 to PH7 I/O PI0/INT0 to PI3/INT3 PI4 to PI7 EXTAL XTAL TEX TX RST Vpp AVREF AVss VDD Vss I/O/input I/O Input Output Input Output Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock generation circuit. Connect a 32.768kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and open TX. Low-level active, system reset. VCC supply for writing of built-in PROM. Under normal operating conditions, connect to VDD. Input Reference voltage input for A/D converter. A/D converter GND. Vcc supply. GND -5- CXP844P16 I/O Circuit Format for Pins Pin Port A Pull-up resistance "0" when reset Port A data Circuit format When reset PA0/AN0 to PA7/AN7 Data bus Port A direction "0" when reset IP Input protection circuit Hi-Z RD (Port A) Port A input selection "0" when reset A/D converter Input multiplexer Pull-up transistors approx. 100k 8 pins Port B Pull-up resistance "0" when reset Port B data PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1 Data bus Port B direction "0" when reset Schmitt input RD (Port B) IP Hi-Z 4 pins Port B CS1 CS0 SI0 SI1 Pull-up transistors approx. 100k Pull-up resistance "0" when reset SCK OUT Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset IP PB2/SCK0 PB5/SCK1 Hi-Z Data bus RD (Port B) Schmitt input 2 pins SCK0, SCK1 in Pull-up transistors approx. 100k -6- CXP844P16 Pin Port B Pull-up resistance SO Output enable Port B output selection "0" at reset Port B data Port B direction "0" when reset Data bus RD (Port B) Circuit format When reset PB4/SO0 PB7/SO1 IP Hi-Z 2 pins Port C Pull-up resistance "0" when reset Port C data Pull-up transistors approx. 100k 2 PC0 to PC7 Port C direction "0" when reset Data bus RD (Port C) 1 High current drive of 12mA possible 2 Pull-up transistors approx. 100k 1 IP Hi-Z 8 pins Port E PE0/EC PE1 PE2/RMC PE3/NMI 4 pins Port E PE4/PWM Schmitt input IP Note : PE1 No schmitt input. EC RMC/NMI Data bus RD (Port E) Hi-Z PWM Port E output selection "0" when reset Port E data H level 1 pin Data bus "1" when reset RD (Port E) -7- CXP844P16 Pin Port E Output enable TO ADJ16K ADJ2K Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus RD (Port B) Circuit format When reset MPX H level When reset. "H level" with about 150k resistor. ADJ signals are frequency division outputs for 32kHz oscillation frequency adjustment ADJ2K provides usage as buzzer output. PE5/TO/ADJ 1 pin Port D Port F Port G PD0 to PD7 PF0 to PF7 PG0 to PG7 PH0 to PH7 PI4 to PI7 Port H Port I Port direction "0" when reset Data bus RD Pull-up transistors approx. 100k IP Pull-up resistance "0" when reset Port data Hi-Z 36 pins Port I Pull-up resistance "0" when reset Port data PI0 to PI3 Port direction "0" when reset Data bus RD INT0 INT1 INT2 INT3 Pull-up transistors approx. 100k Schmitt input IP Hi-Z 4 pins -8- CXP844P16 Pin Circuit format When reset EXTAL XTAL * Diagram shows circuit composition during oscillation. EXTAL IP IP * Feedback resistor is removed during stop and XTAL becomes "High" level. XTAL Oscillation 2 pins TEX TX TEX IP IP * Digram shows circuit composition during oscillation. 2 pins TX * When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively. Oscillation Pull-up resistor RST OP IP Mask option L level 1 pin Schmitt input -9- CXP844P16 Absolute Maximum Ratings Item Symbol VDD Supply voltage Vpp AVSS Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VIN VOUT IOH IOH IOL IOLC IOL Topr Tstg PD Ratings -0.3 to +7.0 -0.3 to +13.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -10 to +75 -55 to +150 600 Unit V V V V V mA mA mA mA mA C C mW Output per pin Total for all output pins Incorporated PROM (Vss = 0V reference) Remarks Value per pin, excluding high current outputs Value per pin2 for high current outputs Total for all output pins 1 VIN and VOUT must not exceed VDD + 0.3V. 2 The high current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. - 10 - CXP844P16 Recommended Operating Conditions Item Symbol Min. 4.5 VDD 3.5 2.7 2.5 Vpp VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr Max. 5.5 5.5 5.5 5.5 V V V V V V V C V Unit (Vss = 0V reference) Remarks High speed mode guaranteed operation range1 Low speed mode guaranteed operation range1 Guaranteed operation range with TEX clock Guaranteed data hold range during STOP 5 2 Hysteresis input3 EXTAL4 2 Hysteresis input3 EXTAL4 Supply voltage Vpp = VDD 0.7VDD 0.8VDD VDD - 0.4 0 0 -0.3 -10 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 1 High speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency demultiplication clock selection. 2 Value for each pin of normal input ports (PA, PB4, PB7, PC, PD, PE1, PF to PH, PI4 to PI7). 3 Value of the following pins: RST, CS0, CS1, SCK0, SCK1, SI0, SI1, EC, RMC, NMI, INT0, INT1, INT2, INT3. 4 Specifies only during external clock input. 5 Vpp and VDD should be set to same voltage. - 11 - CXP844P16 Electrical Characteristics DC Characteristics Item Symbol Pins PA to PD, PE4, PE5, PF to PI PC IIHE IILE IIHT Input current IILT IILR IIL TEX RST1 PA to PD2, PF to PI2 PE0 to PE3 RST1 PA to PD2, PF to PI2 VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V VDD = 5.5V, VI = 0, 5.5V High-speed mode operation (1/2 frequency demultiplier clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD SLEEP mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode IDDS3 Pins other than PE4, PE5, XTAL, TX, AVREF, AVss, VDD, VSS VDD = 5.5V, 10MHz crystal oscillation; and termination of 32kHz oscillation 30 A 1.1 8 mA 18 40 mA EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -10 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 -50 -3.3 Typ. Max. Unit V V V V V A A A A A A A High level VOH output current Low level output current VOL I/O leakage current IIZ 10 A IDD1 IDD2 Power supply current3 IDDS1 400 1000 A IDDS2 9 30 A Input capacity CIN Clock 1MHz 0V for all pins excluding measured pins 10 20 pF 1 RST pin specifies the input current when the product with pull-up resistance has been selected, and specifies the leakage current when the product with no resistance has been selected. (Refer to the products list.) 2 Pins PA to PD, and PF to PI specifies the input current when pull-up resistance has been selected, and specifies the leakage current when no resistance has been selected. 3 When all pins are open. - 12 - CXP844P16 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock input pulse width Event count input clock rise time, fall time Symbol fC Pin (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock application condition) Fig. 3 Fig. 3 10 20 Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX tXL, tXH tCR, tCF tEH, tEL tER, tEF fC tsys + 50 32.768 kHz tTL, tTH tTR, tTF s ms tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing 1/fc VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock application conditions Crystal oscillation Ceramic oscillation External clock 32kHz clock application condition Crystal oscillation EXTAL XTAL EXTAL XTAL TEX TX C1 C2 74HCO4 C1 C2 - 13 - CXP844P16 Fig. 3. Event count clock timing TEX EC 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR (2) Serial transfer Item CS0 SCK0 (CS1 SCK1) delay time CS0 SCK0 (CS1 SCK1) float delay time CS0 SO0 (CS1 SO1) delay time CS0 SO0 (CS1 SO1) float delay time CS0 (CS1) High level width SCK0 (SCK1) cycle time SCK0 (SCK1) High, Low level width SI0 (SI1) input set-up time (for SCK0 ) SI0 (SI1) input hold time (for SCK0 (SCK1 ) ) SCK0 SO0 (SCK1 SO1) delay time Note 1) Symbol Pin (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss reference) Condition Min. Max. Unit tDCSK SCK0 Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) SO0 (SO1) (SO1) (CS1) Chip select transfer mode Chip select transfer mode Chip select transfer mode 1.5tsys + 200 ns 1.5tsys + 200 ns 1.5tsys + 200 ns 1.5tsys + 200 ns tDCSKF SCK0 tDCSO tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 200 2tsys + 200 16000/fc ns ns ns ns ns ns ns ns ns SCK0 Input mode (SCK1) Output mode SCK0 Input mode (SCK1) Output mode SI0 (SI1) SI0 (SI1) SO0 (SO1) SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode tsys + 100 8000/fc - 50 100 200 tsys + 200 100 tsys + 200 100 ns ns tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL. - 14 - CXP844P16 Fig. 4. Serial transfer CH0 timing tWHCS CS0 (CS1) 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 (SCK1) 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 (SI1) Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 (SO1) Output data 0.2VDD - 15 - CXP844P16 (3) A/D converter characteristics (Ta = -10 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = AVSS = 0V -10 4930 160/fADC3 12/fADC3 AVREF AN0 to AN7 Operation mode AVREF IREFS SLEEP mode STOP mode 32kHz operation mode VDD - 0.5 0 0.6 VDD AVREF 1.0 10 10 4990 Symbol Pin Condition Min. Typ. Max. 8 3 70 5050 Unit Bits LSB mV mV s s V V mA A tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current Fig. 5. Definition of A/D converter terms FFH FEH Digital conversion value Linearity error 01H 00H VZT Analog input VFT 1 VZT : Value at which the digital transfer value changes from 00 H to 01H and vice versa. 2 VFT : Value at which the digital transfer value changes from FE H to FFH and vice versa. 3 fADC indicates the below values due to the bit 6 (CKS) of A/D control resistor (address : 00F9H) and the Bit 7 (PCK1) and Bit 6 (PCK0) of clock control resistor (address : 00FFH). CKS PCK1, 0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16) 0 (/2 selection) 1 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 fADC = fC fADC = fC/2 fADC = fC/8 - 16 - CXP844P16 (4) Interruption, reset input Item (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST Condition Min. Max. Unit External interruption High, Low level width tIH tIL tRSL 1 s Reset input Low level width 32/fc s Fig 6. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge) 0.2VDD tIL tIH Fig. 7. RST input timing tRSL RST 0.2VDD - 17 - CXP844P16 Appendix Fig. 8. Recommended oscillation circuit (i) Main clock (ii) Main clock (iii) Sub clock EXTAL XTAL Rd EXTAL XTAL Rd EXTAL TEX XTAL TX Rd C1 C2 C1 C2 C1 C2 Manufacturer Model CSA4.19MG CSA8.00MTZ fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 C1 (pF) C2 (pF) Rd () Circuit example (i) 30 30 0 (ii) MURATA MFG CO., LTD. CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.00MTW RIVER ELETEC CO., LTD. HC-49/U03 8.00 10.00 4.19 12 12 0 (i) 27 20 50 27 20 22 KINSEKI LTD. HC-49/U (-S) 8.00 10.00 0 P3 32.768kHz 1M (iii) Those marked with an asterisk () signify types with built-in ground capacitance (C1, C2). Selection Guide Item Package ROM capacitance Reset pin pull-up resistor Mask product 80-pin plastic QFP 12K bytes/16K bytes Existent/Non-existent CXP844P16Q-180-pin plastic QFP PROM 16K bytes Existent - 18 - CXP844P16 Characteristics curves IDD vs. V DD (fc = 10MHz, Ta = 25C, Typ ical) 20.0 10.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode IDD vs. fc (V DD = 5V , Ta = 25C, Typ ical) 20 IDD - Supply current [mA] 5.0 IDD - Supply current [mA] SLEEP mode 32kHz mode (instruction) 15 1.0 0.5 1/2 dividing mode 10 1/4 dividing mode 0.1 (100A) 0.05 (50A) 32kHz SLEEP mode 1/16 dividing mode 5 0.01 (10A) 2 3 4 5 6 7 0 VDD - Supply voltage [V] SLEEP mode 5 10 fc - System clock [MHz] 1 5 - 19 - CXP844P16 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15 65 40 + 0.4 14.0 - 0.1 17.9 0.4 A 80 25 + 0.2 0.1 - 0.05 0.8 0.12 M + 0.15 0.35 - 0.1 + 0.35 2.75 - 0.15 0 to 10 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE QFP080-P-1420-A - 20 - 0.8 0.2 1 24 16.3 |
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